1. Field of the Invention
The present invention relates to fabrication of semiconductor integrated circuits and, more specifically, to methods for controlling properties of functional layers employed in the fabrication of interconnect structures.
2. Description of the Related Art
Individual circuit elements (e.g., transistors) of an integrated circuit (IC) are appropriately interconnected using an electrically conductive interconnect structure. The process of forming the interconnect structure is usually referred to as backend processing. During backend processing, stacks of conducting and dielectric layers are successively deposited over the semiconductor substrate, patterned, etched, and polished to form electrically conductive pathways between the circuit elements and interface terminals of the IC. The most common electrically conductive materials used in backend processing include aluminum, titanium, nickel, chromium, gold, copper, silver, tungsten, platinum, tantalum, and various alloys thereof, and the most common dielectric materials include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and various combinations/mixtures thereof.
Layer deposition is often accomplished at an elevated temperature with the most common deposition techniques being chemical vapor deposition (CVD), filament evaporation, electron-beam evaporation, flash evaporation, induction evaporation, sputtering, and spin-on coating. When the wafer temperature is subsequently changed, the deposited layers contract or expand in accordance with the values of their respective thermal expansion coefficients. However, because 1) layers adhere to one another and 2) layers exhibit differences in the thermal expansion coefficients, tensile and/or compressive stresses are generated within the layers when the wafer temperature changes. Non-uniform stresses across the layer stack result in stress gradients, which usually cause the wafer to warp (adapt a non-planar shape). Disadvantageously, wafer warpage might affect patterning, etching, and/or polishing of the wafer and might cause topologic defects (e.g., circuit breaks and/or shorts) within the interconnect structure, thereby detrimentally affecting the die yield.